I. Technical Field
The present invention relates to phase lock loop frequency synthesizers. More specifically, the present invention relates to a novel and improved method of phase lock loop frequency synthesis whereby the reference signal for the phase lock loop is provided by a direct digital synthesizer (DDS) capable of generating any one of a plurality of periodic reference signals, each having a different periodic frequency.
II. Background Art
Conventional frequency synthesis is often accomplished with the use of one or more phase lock loops. A phase lock loop is designed to output a signal at a range of frequencies with frequency resolution, or step size, equal to the loop reference frequency.
Conventional phase lock loops synthesize a frequency by using a control voltage to drive a voltage controlled oscillator (VCO) which generates a signal of a frequency near the desired frequency. A frequency divider is used to divide the VCO signal output frequency by an integer value. The integer value is chosen such that if the VCO were generating exactly the desired frequency, the resultant divided frequency signal would be exactly the same frequency as a reference frequency.
The divided frequency signal is input along with the reference frequency signal to a phase detector. The phase detector compares the frequencies of the two input signals and outputs a voltage proportional to the difference in frequency of the two input signals. The output of the phase detector is coupled through a loop filter, necessary to insure loop stability, where it is input to the VCO as the control voltage. Accordingly, the output signal from the VCO is adjusted to a frequency exactly that of the desired frequency.
The performance of a phase lock loop is related to several factors including (1) the frequency of the reference signal, (2) the magnitude of the divisor necessary to divide the output frequency down to the reference frequency, and (3) the bandwidth of the loop filter. The frequency of the reference signal dictates the frequency resolution, or step size of the loop, i.e. the smaller the reference frequency, the greater the frequency resolution. The magnitude of the loop divisor has great impact on the noise performance of the loop. As such, any phase noise or spurious noise in the reference frequency will appear in the loop output having its original magnitude multiplied by the loop divisor. The bandwidth of the loop filter, which is normally five to ten percent of the reference frequency, impacts the speed with which the loop can settle on a new frequency. Thus the narrower the loop filter bandwidth, the slower the loop will be able to settle on the new frequency.
These performance factors suggest the difficulty in designing a phase lock loop with narrow channel spacing, while maintaining a broad range of output frequencies. If the VCO output signal frequency is very large relative to the reference signal frequency (and therefore the frequency step size), the loop divisor must be very large. Therefore, any noise in the reference signal will appear on the loop output multiplied by a very large value. For this reason, conventional frequency synthesizers often comprise two or more phase lock loops. Each phase lock loop is of differing frequency resolution and corresponding output frequency range. In such a configuration the output of a coarse resolution loop, with a relatively large frequency range, can be mixed with the output of a fine resolution loop with a narrow frequency range. This combination of coarse and fine resolution loops results in a loop which is capable of providing a narrow frequency step size over a broad range of frequencies.
There are many disadvantages to the conventional multiple loop phase lock loop synthesizer. Increasing the number of loops increases the quantity and cost of required hardware, as well as the power and space requirements of the synthesizer. Also, although employing a separate fine resolution loop of limited output range narrows frequency step size, there remains a tradeoff between this resolution and switching speed. This tradeoff exists because the bandwidth of the loop filter, which dictates the switching speed, can be no more than five to ten percent of the reference frequency (and therefore the frequency step size). A further disadvantage of a multiple loop synthesizer is the mixing of the loop outputs creates substantial undesirable wideband spurious noise in the resultant output signal.
It is therefore an object of the present invention to provide a novel and improved phase lock loop frequency synthesizer which requires substantially less hardware, space, and power than the conventional phase lock loop and multi-loop frequency synthesizer.
It is a further object of the present invention to provide a novel and improved phase lock loop frequency synthesizer which requires only one phase lock loop, yet has substantially greater frequency resolution and frequency range than the conventional frequency synthesizer.
Yet another object of the present invention is to provide a novel and improved phase lock loop frequency synthesizer which has substantially faster frequency switching time than a conventional frequency synthesizer of comparable frequency resolution and frequency range.
It is a further object of the present invention to provide a novel and improved phase lock loop frequency synthesizer which has substantially less wideband spurious noise in its output than the conventional multi-loop frequency synthesizer of comparable frequency resolution and frequency range.